Fourth Quarter Enterprises

Services

SI, PI, and EMC engineering - in writing, with margin.

We deliver signal integrity, power integrity, and EMC analysis for high-speed digital boards on mission-critical programs - from pre-layout topology through post-layout sign-off and lab correlation.

Primary practices

Engineering engagements

Pre-Layout SI Analysis

Get the topology, stackup, and channel budget right before layout begins - when changes are still cheap.

What's included

  • Interface selection review: DDR4/5, LPDDR5, PCIe Gen4/5/6, CXL, 10/25/100G Ethernet, JESD204B/C, SerDes
  • Stackup and impedance planning with controlled-impedance dielectric selection
  • IBIS and IBIS-AMI model qualification, encrypted-model handling under NDA
  • Channel budgeting: insertion loss, return loss, ISI, and jitter allocation with margin
  • Topology and termination trade studies with routed-length constraints for layout

Post-Layout Verification

Independent sign-off analysis on real routed data before you commit to fabrication.

What's included

  • 3D full-wave EM extraction of vias, breakout regions, connectors, and reference-plane transitions
  • S-parameter passivity/causality checks and channel compliance against JEDEC / PCI-SIG / IEEE masks
  • Statistical eye analysis, jitter and BER budgeting, crosstalk aggression scenarios
  • Return-path continuity and reference-plane review, split-plane and stitching-via recommendations
  • Written sign-off report with margins, assumptions, tool versions, and reproducible project files

Power Integrity & EMC

Clean rails and predictable emissions for boards that have to pass qualification the first time.

What's included

  • Target-impedance derivation from transient current profiles and package models
  • Decoupling network optimization: value, placement, mounting inductance, and quantity
  • Plane-resonance and PDN cavity analysis with anti-resonance mitigation
  • Radiated-emissions risk review for MIL-STD-461, DO-160, and CISPR / FCC intent
  • Return-current and shielding recommendations for mixed analog/digital boards

How engagements work

01
Scope

NDA-first scoping call to define interfaces, mission class, deliverables, and schedule.

02
Model

Build the pre-layout channel model: stackup, topology, IBIS/AMI, and jitter budget.

03
Verify

Extract the routed channel, correlate to the pre-layout budget, and resolve deltas before tape-out.

04
Sign off

Deliver a written report with compliance margins, waivers, and open risks. Optional lab correlation.

Interfaces & standards

Coverage across the modern high-speed digital stack.

DDR4 / DDR5 / LPDDR5PCIe Gen4 / Gen5 / Gen6CXL 2.0 / 3.010G / 25G / 100G / 400G EthernetJESD204B / JESD204CUSB 3.2 / USB4 / ThunderboltMIPI D-PHY / C-PHYCustom SerDes up to 112G PAM4

Supporting practice

Design Review & Bring-Up Support

Available for existing engagement clients: schematic and layout review passes, DDR training-margin interpretation, PCIe LTSSM debug, TDR/S-parameter measurement reviews, and structured bring-up support during first-article testing.

Ready to de-risk your next board?

A short scoping call is the fastest way to determine which practice - pre-layout, post-layout, or PI/EMC - is the right entry point for your program.

Request an engagement